2012-07-17 01:05:27 +02:00
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#include <inttypes.h>
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <util/delay.h>
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#include <stdlib.h>
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#include "main.h"
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2012-07-26 01:50:48 +02:00
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volatile uint8_t sample_pending;
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2012-07-26 01:34:49 +02:00
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2012-07-26 01:26:45 +02:00
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// sample rate is 8M / (5 * 64) = 25000
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2012-08-06 00:16:17 +02:00
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2012-07-26 01:26:45 +02:00
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enum {
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synth_channel_count = 2
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};
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typedef struct {
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uint16_t phase;
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uint16_t speed;
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} synth_channel_t;
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typedef struct {
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synth_channel_t channels[synth_channel_count];
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uint16_t output;
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} synth_t;
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2012-07-26 01:34:49 +02:00
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2012-07-26 01:26:45 +02:00
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static synth_t synth;
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2012-08-06 00:16:17 +02:00
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uint8_t counter = 0;
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uint8_t pulsewidth = 0;
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uint8_t maxcounter = 0xFF;
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uint16_t pulsecounter = 0;
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2012-07-26 01:26:45 +02:00
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static void synth_init(void)
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{
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// some test values
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synth.channels[0].phase = 0;
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synth.channels[0].speed = 1153;
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synth.channels[1].phase = 0;
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2012-07-26 02:27:12 +02:00
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synth.channels[1].speed = 1728;
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2012-07-26 01:26:45 +02:00
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}
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static inline void synth_mix(void)
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{
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synth.output = 0;
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2012-07-26 01:50:48 +02:00
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for (int i = 0; i < synth_channel_count; i++) {
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synth_channel_t *chan = &synth.channels[i];
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2012-07-26 01:26:45 +02:00
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chan->phase += chan->speed;
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2012-07-26 02:19:59 +02:00
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synth.output += (chan->phase >> 8) & 0xff;
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2012-07-26 01:26:45 +02:00
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}
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2012-07-26 01:34:49 +02:00
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}
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static void init_sampletimer(void)
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{
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// Timer 0
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//
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//set timer0 to CTC & prescaler 64 == 125k
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2012-07-26 01:50:48 +02:00
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TCCR0A = (1 << WGM01);
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TCCR0B = (1 << CS00) | (1 << CS01);
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2012-07-26 01:34:49 +02:00
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//count up to 5 :
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2012-08-06 00:16:17 +02:00
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OCR0A = 3;
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TCNT0=0;
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2012-07-26 01:34:49 +02:00
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//enable interrupt
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2012-08-06 00:16:17 +02:00
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TIMSK0 |= (1<<OCIE0A);
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2012-07-26 01:34:49 +02:00
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}
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2012-07-18 15:55:20 +02:00
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static inline void init_pwm(void)
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{
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2012-08-05 22:17:27 +02:00
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//PB2 set to output:
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2012-07-26 01:50:48 +02:00
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DDRB |= (1 << PORTB2);
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2012-08-05 22:13:43 +02:00
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OCR1B = 0x001F; //preselect some default
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2012-08-06 00:16:17 +02:00
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ICR1 = 0x003F; // TOP-wert
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2012-07-18 16:12:48 +02:00
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2012-07-26 01:50:48 +02:00
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TCCR1A = (1 << COM1B1) | (1 << WGM11); // only b-chan , fastpwm (mode 14)
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TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10); //Fastpwm, no prescale
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2012-07-18 16:12:48 +02:00
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2012-08-06 00:16:17 +02:00
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//TIMSK1 |= (1 << OCIE1B); //enable timer 1 Output compare
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2012-07-26 01:50:48 +02:00
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return;
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2012-07-18 02:34:15 +02:00
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}
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2012-07-18 15:55:20 +02:00
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static void init_leds(void)
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2012-07-17 01:05:27 +02:00
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{
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//enable LED channels as output
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2012-07-18 15:55:20 +02:00
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DDRC |= (1 << PORTC0) | (1 << PORTC2) | (1 << PORTC3) | (1 << PORTC1);
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PORTC = 1; //one led is on...
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return;
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}
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2012-07-18 02:34:15 +02:00
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2012-07-18 15:55:20 +02:00
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inline void setleds(uint8_t state)
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{
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//set leds according to
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2012-07-26 02:19:59 +02:00
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PORTC |= (state | 0b00001111);
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PORTC &= ~(state | 0b11110000);
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2012-07-18 15:55:20 +02:00
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return;
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}
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2012-07-17 01:05:27 +02:00
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2012-07-18 15:55:20 +02:00
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static void init_motor(void)
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{
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//vibration motor on B1:
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DDRB |= (1 << PORTB1);
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2012-07-17 01:05:27 +02:00
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2012-07-18 15:55:20 +02:00
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}
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2012-07-18 02:34:15 +02:00
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2012-07-17 01:05:27 +02:00
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2012-08-06 00:16:17 +02:00
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2012-07-18 15:55:20 +02:00
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int main(void)
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{
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2012-07-26 01:26:45 +02:00
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//hardware initialisation:
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2012-07-18 15:55:20 +02:00
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init_leds();
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2012-08-06 00:16:17 +02:00
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//init_motor();
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2012-07-18 15:55:20 +02:00
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init_pwm();
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2012-07-26 02:20:55 +02:00
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init_sampletimer();
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2012-08-06 00:16:17 +02:00
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//sample_pending = 0;
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//synth_init();
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//OCR1B = 0x00F0;
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2012-07-26 01:50:48 +02:00
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sei();
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2012-08-06 00:16:17 +02:00
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while(1){
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//PORTC ^= 0b1;
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}
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2012-08-05 22:17:27 +02:00
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while(1);
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2012-07-26 02:19:59 +02:00
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while(1) {
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2012-07-26 01:50:48 +02:00
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while (0 == sample_pending) ;
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sample_pending = 0;
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synth_mix();
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}
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2012-07-18 15:55:20 +02:00
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//never get here
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2012-07-26 01:26:45 +02:00
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return 0;
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2012-07-18 15:55:20 +02:00
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}
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2012-08-05 22:13:43 +02:00
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2012-08-06 00:16:17 +02:00
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/*ISR(TIMER1_COMPB_vect)
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2012-08-05 22:13:43 +02:00
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{
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2012-08-06 00:16:17 +02:00
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OCR1B = 0x00F0;
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} */
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2012-08-05 22:13:43 +02:00
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//25kHz
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2012-08-06 00:16:17 +02:00
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ISR(TIMER0_COMPA_vect)
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2012-08-05 22:13:43 +02:00
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{
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2012-08-06 00:16:17 +02:00
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counter++;
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if (counter > maxcounter){
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counter = 0;
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};
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pulsecounter++;
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if (pulsecounter > 0x0200){
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pulsecounter = 0;
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pulsewidth++;
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if (pulsewidth > maxcounter){
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pulsewidth = 0;
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}
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}
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OCR1B = ((counter > pulsewidth) ? maxcounter : 0x00);
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//OCR1B = counter;
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//OCR1B = OCR1B + 4;
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if (OCR1B > 0x007F) {
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// OCR1B = 0x00F;
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}
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PORTC ^= 0b01;
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//ICR1 = synth.output;
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//sample_pending = 1;
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2012-08-05 22:13:43 +02:00
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}
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2012-08-06 00:16:17 +02:00
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