mods before merge
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@ -32,7 +32,7 @@ static synth_t synth;
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ISR(TIMER0_OVF_vect)
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{
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PORTC ^= 0b1;
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ICR1 = synth.output;
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OCR1B = (++OCR1B % 0x1000);
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sample_pending = 1;
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}
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@ -67,17 +67,16 @@ static void init_sampletimer(void)
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TCCR0B = (1 << CS00) | (1 << CS01);
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//count up to 5 :
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OCR0A = 5;
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//enable interrupt
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TIMSK0 |= (1 << TOIE0);
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}
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static inline void init_pwm(void)
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{
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//PB1 set to output:
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//PB2 set to output:
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DDRB |= (1 << PORTB2);
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OCR1B = 0xefff; //preselect some default
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ICR1 = 0xffff; // TOP-wert
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OCR1B = 0x100; //preselect some default
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ICR1 = 0x1000; // TOP-wert
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TCCR1A = (1 << COM1B1) | (1 << WGM11); // only b-chan , fastpwm (mode 14)
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TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10); //Fastpwm, no prescale
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@ -108,24 +107,6 @@ static void init_motor(void)
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}
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static void stupid_pwmtest(void)
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{
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uint8_t i, t, r;
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ICR1 = 0xAA00;
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t = r = 1;
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for (;;) {
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t = (r) ? (t + 1) : (t - 1);
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ICR1 = (t << 7);
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if (t == 0)
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r ^= 1;
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for (i = 1; i < 100; i++)
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__asm("nop");
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}
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return; //never
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}
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int main(void)
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{
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@ -140,6 +121,7 @@ int main(void)
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sei();
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while(1);
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while(1) {
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while (0 == sample_pending) ;
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sample_pending = 0;
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