aw/pentabug
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commit for sync

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This commit is contained in:
bigalex 2012-08-05 22:13:43 +02:00
parent b325262268
commit 97fd29480d
1 changed files with 19 additions and 10 deletions
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29
firmware/main.c
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@ -28,13 +28,6 @@ typedef struct {
static synth_t synth; static synth_t synth;
//25kHz
ISR(TIMER0_OVF_vect)
{
PORTC ^= 0b1;
ICR1 = synth.output;
sample_pending = 1;
}
static void synth_init(void) static void synth_init(void)
{ {
@ -76,12 +69,13 @@ static inline void init_pwm(void)
{ {
//PB1 set to output: //PB1 set to output:
DDRB |= (1 << PORTB2); DDRB |= (1 << PORTB2);
OCR1B = 0xefff; //preselect some default OCR1B = 0x001F; //preselect some default
ICR1 = 0xffff; // TOP-wert ICR1 = 0x00FF; // TOP-wert
TCCR1A = (1 << COM1B1) | (1 << WGM11); // only b-chan , fastpwm (mode 14) TCCR1A = (1 << COM1B1) | (1 << WGM11); // only b-chan , fastpwm (mode 14)
TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10); //Fastpwm, no prescale TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10); //Fastpwm, no prescale
TIMSK1 |= (1 << OCIE1B); //enabke timer 1 Output compare
return; return;
} }
@ -137,7 +131,7 @@ int main(void)
init_sampletimer(); init_sampletimer();
sample_pending = 0; sample_pending = 0;
synth_init(); synth_init();
//OCR1B = 0x00F0;
sei(); sei();
while(1) { while(1) {
@ -149,3 +143,18 @@ int main(void)
//never get here //never get here
return 0; return 0;
} }
ISR(TIMER1_COMPB_vect)
{
//OCR1B = 0x00F0;
}
//25kHz
ISR(TIMER0_OVF_vect)
{
OCR1B = 0x00F0;
PORTC ^= 0b1;
ICR1 = synth.output;
sample_pending = 1;
}