From 97fd29480dbc7bbecfd82e60e8679df9c79c5ed3 Mon Sep 17 00:00:00 2001 From: bigalex Date: Sun, 5 Aug 2012 22:13:43 +0200 Subject: [PATCH] commit for sync --- firmware/main.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/firmware/main.c b/firmware/main.c index 16ccff9..d6ae7de 100644 --- a/firmware/main.c +++ b/firmware/main.c @@ -28,13 +28,6 @@ typedef struct { static synth_t synth; -//25kHz -ISR(TIMER0_OVF_vect) -{ - PORTC ^= 0b1; - ICR1 = synth.output; - sample_pending = 1; -} static void synth_init(void) { @@ -76,12 +69,13 @@ static inline void init_pwm(void) { //PB1 set to output: DDRB |= (1 << PORTB2); - OCR1B = 0xefff; //preselect some default - ICR1 = 0xffff; // TOP-wert + OCR1B = 0x001F; //preselect some default + ICR1 = 0x00FF; // TOP-wert TCCR1A = (1 << COM1B1) | (1 << WGM11); // only b-chan , fastpwm (mode 14) TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10); //Fastpwm, no prescale + TIMSK1 |= (1 << OCIE1B); //enabke timer 1 Output compare return; } @@ -137,7 +131,7 @@ int main(void) init_sampletimer(); sample_pending = 0; synth_init(); - +//OCR1B = 0x00F0; sei(); while(1) { @@ -149,3 +143,18 @@ int main(void) //never get here return 0; } + +ISR(TIMER1_COMPB_vect) +{ + //OCR1B = 0x00F0; +} + +//25kHz +ISR(TIMER0_OVF_vect) +{ + OCR1B = 0x00F0; + PORTC ^= 0b1; + ICR1 = synth.output; + sample_pending = 1; +} +